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【【简单systyem verilog 语言学习使用一— adder加法器 】】

adder.v

module adder( input          [3 : 0]       a    ,input          [3 : 0]       b    ,output         [3 : 0]       sum  ,output                       carry  
); assign  {carry,sum } = a + b ;endmodule  

adder_tb.sv

class input1   ;rand bit [3 : 0]  a  ;constraint in_cons { a > 0 ; a < 15; }function void display() ;$write("rand number a is %4d", a) ;endfunctionendclassclass input2 ;rand bit [3 : 0]  b  ;constraint in_cons { b > 0 ; b < 15; }function void display() ;$write("rand number b is %4d", b) ;endfunctionendclassmodule   test  ;//对 类 进行例化input1  a_inst  ;input2  b_inst  ;logic [3 : 0]  a,b , sum ;logic  carry  ;adder u_adder(.a    ( a    ),.b    ( b    ),.sum  ( sum  ),.carry  ( carry  ));// 开始初始化initialbegina_inst = new();b_inst = new();assert (a_inst.randomize())  ;assert (b_inst.randomize())  ;a = a_inst.a  ;b = b_inst.b  ;a_inst.display() ;b_inst.display() ;#5$display("Sum=%4d,Carry=%1b", sum, carry);endendmodule