Design Compiler:检查时序问题(check_timing命令)

📅 2026/8/25 10:14:25
Design Compiler:检查时序问题(check_timing命令)
相关阅读Design Compilerhttps://blog.csdn.net/weixin_45791458/category_12738116.html?spm1001.2014.3001.5482check_timing命令可用来检查设计中的各种时序问题例如时钟定义端口约束等本文将详细讨论该命令的使用方式及每一个检查项的具体含义。check_timing命令的BNF范式有关BNF范式可以参考以往文章为check_timing [-overlap_tolerance minimum_distance] [-multiple_clock] [-retain] [-override_defaults check_list] [-include check_list] [-exclude check_list] [-sdc_runtime] //注该命令的选项和参数顺序任意默认检查列表由timing_check_defaults变量指定默认值为generated_clock loops no_input_delay unconstrained_endpoints pulse_clock_cell_type no_driving_cell partial_input_delay如果要重新指定检查列表使用-override_defaults选项如果要向检查列表中添加或减少检查项使用-include或-exclude选项。-sdc_runtime选项用于报告SDC相关的运行时间问题具体使用方法可见下面的博客。Design CompilerSDC相关运行时间问题的报告和修复https://blog.csdn.net/weixin_45791458/article/details/155578884?spm1001.2014.3001.5501下面将列出所有的检查项以及其具体说明。-overlap_tolerance当设计中包含双电平触发的主从锁存器该选项用于指定主时钟关闭沿与从时钟开启沿可以允许的最小时间如果该距离小于指定值工具会发出警告。-multiple_clock和-retain这两个选项都可以用相应检查项等效表示因此在后文统一说明。检查项clock_crossing在多时钟域存在的情况下检查时钟之间的交互关系。如果一个时钟发射的一条或多条时序路径被其他时钟捕获则会在报告中生成一条记录。当两个时钟之间的所有时序路径都是虚假路径或者这两个时钟是互斥(exclusive)时钟或异步(asynchronous)时钟则该对时钟会被标记为*当两个时钟之间的部分时序路径都是虚假路径则该对时钟会被标记为#。clock_no_period当设计中存在没有指定时钟周期的时钟工具会发出警告。data_check_multiple_clock当使用set_data_check命令设置了数据到数据检查时如果参考引脚处信号被多个时钟发射工具会发出警告。data_check_no_clock当使用set_data_check命令设置了数据到数据检查时如果参考引脚处的信号没有时钟发射工具会发出警告。gated_clock当在门控时钟优化时产生了离散门控时钟单元包括Latch-Free和Latch-Based工具会发出警告。generated_clock检查设计中定义的生成时钟并在出现以下情况时报告1、没有任何时钟可以传播到生成时钟源引脚找不到master clock。2、生成时钟源引脚处的master clock不存在任何通往生成时钟源对象的时序路径。3、多个生成时钟形成环路。4、定义生成时钟时没有指定-master_clock和-add选项使用这两个选项是一个好习惯。5、当生成时钟源引脚的master clock也是生成时钟且它找不到自己的master clock。有关生成时钟的更多介绍可见下面这篇博客所示。SDC命令详解使用create_generated_clock命令进行约束上https://blog.csdn.net/weixin_45791458/article/details/134236547?ops_request_misc%257B%2522request%255Fid%2522%253A%2522355ac9663f111e8ce32150ab78731d52%2522%252C%2522scm%2522%253A%252220140713.130102334.pc%255Fblog.%2522%257Drequest_id355ac9663f111e8ce32150ab78731d52biz_id0utm_mediumdistribute.pc_search_result.none-task-blog-2~blog~first_rank_ecpm_v1~rank_v31_ecpm-1-134236547-null-null.nonecaseutm_termgeneratedspm1018.2226.3001.4450generic当设计中存在GTECH格式或者说Generic Technology格式的单元工具会发出警告有关GTECH的更多介绍可见下面这篇博客所示。HDL Compiler工具简介https://blog.csdn.net/weixin_45791458/article/details/145590417?ops_request_misc%257B%2522request%255Fid%2522%253A%2522a3f94725a881dfe64d36fd922b4d93cb%2522%252C%2522scm%2522%253A%252220140713.130102334.pc%255Fblog.%2522%257Drequest_ida3f94725a881dfe64d36fd922b4d93cbbiz_id0utm_mediumdistribute.pc_search_result.none-task-blog-2~blog~first_rank_ecpm_v1~rank_v31_ecpm-1-145590417-null-null.nonecaseutm_termgtechspm1018.2226.3001.4450ideal_clocks当设计中存在理想时钟工具会发出警告有关理想时钟的更多介绍可见下面这篇博客所示。静态时序分析ideal_clock、propagated_clock以及generated_clock的关系及其延迟计算规则一https://blog.csdn.net/weixin_45791458/article/details/139998035?ops_request_misc%257B%2522request%255Fid%2522%253A%2522c9955013107d9893c02109990417191e%2522%252C%2522scm%2522%253A%252220140713.130102334.pc%255Fblog.%2522%257Drequest_idc9955013107d9893c02109990417191ebiz_id0utm_mediumdistribute.pc_search_result.none-task-blog-2~blog~first_rank_ecpm_v1~rank_v31_ecpm-2-139998035-null-null.nonecaseutm_term%E7%90%86%E6%83%B3%E6%97%B6%E9%92%9Fspm1018.2226.3001.4450ideal_timing当使用set_ideal_latency或set_ideal_transition命令设置了非理想网络的理想延迟值和理想转换时间时工具会发出警告。loops当设计中存在组合逻辑环(Timing Loop)时工具会发出警告。multiple_clock当多个时钟到达同一个触发器的时钟引脚时工具会发出警告。net_no_driving_info当某条线网具有耦合寄生参数但没有驱动引脚或者其驱动引脚上不存在时序弧时工具会发出警告。no_clock当触发器的时钟引脚没有时钟到达时工具会发出警告有关时钟创建的更多介绍可见下面这篇博客所示。SDC命令详解使用create_clock命令进行约束https://blog.csdn.net/weixin_45791458/article/details/134217796?ops_request_misc%257B%2522request%255Fid%2522%253A%25222cb0cda66fb2acd9f9e4985225c30ef8%2522%252C%2522scm%2522%253A%252220140713.130102334.pc%255Fblog.%2522%257Drequest_id2cb0cda66fb2acd9f9e4985225c30ef8biz_id0utm_mediumdistribute.pc_search_result.none-task-blog-2~blog~first_rank_ecpm_v1~rank_v31_ecpm-1-134217796-null-null.nonecaseutm_termcreate_clockspm1018.2226.3001.4450no_driving_cell当某条具有耦合寄生参数的线网的驱动端口没有使用set_driving_cell命令指定驱动单元时工具会发出警告因为这会对串扰分析产生影响有关set_driving_cell命令的使用可见下面这篇博客所示。SDC命令详解使用set_driving_cell命令进行约束https://blog.csdn.net/weixin_45791458/article/details/136244490?ops_request_misc%257B%2522request%255Fid%2522%253A%25222f5b1950c25c88d69e3d8d353384e4fc%2522%252C%2522scm%2522%253A%252220140713.130102334.pc%255Fblog.%2522%257Drequest_id2f5b1950c25c88d69e3d8d353384e4fcbiz_id0utm_mediumdistribute.pc_search_result.none-task-blog-2~blog~first_rank_ecpm_v1~rank_v31_ecpm-1-136244490-null-null.nonecaseutm_termset_driving_cellspm1018.2226.3001.4450no_input_delay当没有使用set_input_delay命令对输入端口进行约束且不存在默认时钟timing_input_port_default_clock变量设置为false时工具会发出警告。partial_input_delay当只使用set_input_delay命令对输入端口在最大或最小条件之一进行约束时工具会发出警告有关set_input_delay命令的使用可见下面这篇博客所示。SDC命令详解使用set_input_delay命令进行约束https://blog.csdn.net/weixin_45791458/article/details/136176375?ops_request_misc%257B%2522request%255Fid%2522%253A%252237adc4c55770bc8383253fb8e005bcec%2522%252C%2522scm%2522%253A%252220140713.130102334.pc%255Fblog.%2522%257Drequest_id37adc4c55770bc8383253fb8e005bcecbiz_id0utm_mediumdistribute.pc_search_result.none-task-blog-2~blog~first_rank_ecpm_v1~rank_v31_ecpm-1-136176375-null-null.nonecaseutm_termset_input_delayspm1018.2226.3001.4450pulse_clock_cell_type已废弃当使用set_pulse_clock_cell命令定义的脉冲生成器与其在库中定义的脉冲类型不匹配时工具会发出警告。retain存储器在库特征化时的时钟到输出时序弧可能有两条一条为常见的表征最大延迟的clk2q时序弧另一条则为表征最小延迟的retain时序弧一般用在保持时间分析。当retain时序弧的延迟大于clk2q时序弧时工具会发出警告有关retain时序弧的更多信息可见下面这篇Solvnet文章所示。For What is a RETAIN Timing Arc Used?https://solvnetplus.synopsys.com/s/article/For-What-is-a-RETAIN-Timing-Arc-Used-1576002492653关于retain时序弧的更多内容可以参考下面的博客。Library Compiler时序弧建模与约束全解析三https://blog.csdn.net/weixin_45791458/article/details/160740267?spm1001.2014.3001.5501unconstrained_endpoints当某些未被设置为虚假路径的时序路径未被约束一般而言只有起点和终点都被时钟约束了时序路径才被视为已约束时工具会发出警告有关时序路径的约束可见下面这篇博客所示。静态时序分析典型与非典型时序路径的约束详解一https://blog.csdn.net/weixin_45791458/article/details/136521221?ops_request_misc%257B%2522request%255Fid%2522%253A%2522e13f9b1940b738a48080c4bd44feb1f2%2522%252C%2522scm%2522%253A%252220140713.130102334.pc%255Fblog.%2522%257Drequest_ide13f9b1940b738a48080c4bd44feb1f2biz_id0utm_mediumdistribute.pc_search_result.none-task-blog-2~blog~first_rank_ecpm_v1~rank_v31_ecpm-1-136521221-null-null.nonecaseutm_term%E8%B5%B7%E7%82%B9%E5%92%8C%E7%BB%88%E7%82%B9%E7%BA%A6%E6%9D%9Fspm1018.2226.3001.4450object_collection当设置约束时未使用集合而是使用字符串或列表时工具会发出警告有关集合的使用可见下面这篇博客所示。SDC命令详解使用集合(Collection)而不是字符串(String)/列表(List)作为命令参数https://blog.csdn.net/weixin_45791458/article/details/147144571?ops_request_misc%257B%2522request%255Fid%2522%253A%2522d42ac23e00ecbb10a76e0f26a890432b%2522%252C%2522scm%2522%253A%252220140713.130102334.pc%255Fblog.%2522%257Drequest_idd42ac23e00ecbb10a76e0f26a890432bbiz_id0utm_mediumdistribute.pc_search_result.none-task-blog-2~blog~first_rank_ecpm_v1~rank_v31_ecpm-1-147144571-null-null.nonecaseutm_termcollectionspm1018.2226.3001.4450related_clock当两个生成时钟的master clock相同且使用了set_false_path或set_clock_groups命令指定了两个生成时钟之间的关系时工具会发出警告有关set_false_path命令的使用可见下面这篇博客所示。SDC命令详解使用set_fasle_path命令进行约束https://blog.csdn.net/weixin_45791458/article/details/136490703?ops_request_misc%257B%2522request%255Fid%2522%253A%2522ddf85b467f7993c4d451b2bae24cee01%2522%252C%2522scm%2522%253A%252220140713.130102334.pc%255Fblog.%2522%257Drequest_idddf85b467f7993c4d451b2bae24cee01biz_id0utm_mediumdistribute.pc_search_result.none-task-blog-2~blog~first_rank_ecpm_v1~rank_v31_ecpm-1-136490703-null-null.nonecaseutm_termset_false_pathspm1018.2226.3001.4450multicycle_path当使用set_multicycle_path命令设置多周期路径时如果时序路径的发射时钟快于捕获时钟且使用了-end选项或者时序路径的发射时钟慢于捕获时钟且使用了-start选项工具会发出警告有关set_multicycle_path命令的使用可见下面这篇博客所示。SDC命令详解使用set_multicycle_path命令进行约束https://blog.csdn.net/weixin_45791458/article/details/136591151?ops_request_misc%257B%2522request%255Fid%2522%253A%252258a3085fcdf1ee50648c000b654af61a%2522%252C%2522scm%2522%253A%252220140713.130102334.pc%255Fblog.%2522%257Drequest_id58a3085fcdf1ee50648c000b654af61abiz_id0utm_mediumdistribute.pc_search_result.none-task-blog-2~blog~first_rank_ecpm_v1~rank_v31_ecpm-1-136591151-null-null.nonecaseutm_termset_multicycle_pathspm1018.2226.3001.4450create_clock当一个时钟被定义在另一个时钟的传播路径上指的是使用create_clock命令而不是create_generated_clock命令工具会发出警告。set_case_analysis当两条set_case_analysis命令导致一个引脚的值出现冲突时工具会发出警告有关set_case_analysis命令的使用可见下面这篇博客所示。SDC命令详解使用set_case_analysis命令进行约束https://blog.csdn.net/weixin_45791458/article/details/136405802?ops_request_misc%257B%2522request%255Fid%2522%253A%2522f5106b4b6af169e260581527c392de41%2522%252C%2522scm%2522%253A%252220140713.130102334.pc%255Fblog.%2522%257Drequest_idf5106b4b6af169e260581527c392de41biz_id0utm_mediumdistribute.pc_search_result.none-task-blog-2~blog~first_rank_ecpm_v1~rank_v31_ecpm-1-136405802-null-null.nonecaseutm_termset_case_analysisspm1018.2226.3001.4450