2.2预定义门构建二选一选择器（VIVADO）
结构级硬件描述module structual_design (output y_out,input sel_in,input a_in,input b_in
);logic temp_1 ,tmp_2,tmp_3;and u1(tmp_2, sel_in,a_in);and u2(tmp_3, tmp_1, b_in);not u3(tmp_1,sel_in);or u4(y_out, tmp_2, tmp_3);
endmoduleRTL ANALYSISSYNTHESIS
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