从零开始设计riscv cpu记录之四
ex.v模块的代码现在写的是简单的逻辑不涉及CSR模块、控制模块等复杂逻辑其中乘除法都是单周期实现后边再实现多周期除法写的思路还是首先弄清ex模块和哪些模块有联系交互的端口列出来input wire[DW-1:0]inst_i,input wire[AW-1:0]inst_addr_i,input wire reg_we_i,input wire[4:0]reg_waddr_i,input wire[DW-1:0]op1_i,input wire[DW-1:0]op2_i,input wire[DW-1:0]op1_jump_i,input wire[DW-1:0]op2_jump_i,output reg reg_we_o,output reg[4:0]reg_waddr_o,output reg[DW-1:0]reg_wdata_o,// to memoutput reg mem_we_o,output reg[AW-1:0]mem_addr_o,output reg[DW-1:0]mem_wdata_o,// jumpoutput reg jump_flag_o,output reg[AW-1:0]jump_addr_o,//for storeinput wire[DW-1:0]reg2_rdata_i然后再去想ex模块要干什么、输出什么最后开始写就行了写的技巧在always块的开头罗列所有输出信号并赋予初值。见代码always(*)begin reg_we_oreg_we_i;reg_waddr_oreg_waddr_i;reg_wdata_oZeroWord;mem_we_oWriteDisable;mem_addr_oZeroWord;mem_wdata_oZeroWord;jump_flag_oJumpDisable;jump_addr_oZeroWord;后边的逻辑 end开始想怎么写ex模块对每条指令完成运算id模块已经把操作数准备好了就是op1_i op2_i 涉及到跳转的要计算跳转地址用到op1_jump_i、op2_jump_i那就每条指令展开因为每条指令做的事不一样。用if-else显然不适合因为指令挺多且没有先后顺序还是用case更合适弄清楚每条指令功能改变的是哪几个输出信号在分支里写出来就完事比如lui指令其功能是把20为立即数装进rd的高20位。id模块已经准备好操作数id.v:case(opcode)INST_TYPE_LUI:begin reg_we_oWriteEnable;reg_waddr_ord;op1_o{inst_i[31:12],12h0};op2_oZeroWord;end...........省去后边的代码那就很明确了在ex.v中的LUI指令是要把op1_iop2_i的和写回rd寄存器。case(opcode)INST_TYPE_LUI:begin reg_wdata_oop1_iop2_i;end由于默认值reg_we_o reg_we_i ; reg_waddr_o reg_waddr_i ;所以知在LUI分支里边设置reg_wdata_o即可。别的指令也是如此。重复即可以下是ex.v的全部代码timescale1ns/1ps//////////////////////////////////////////////////////////////////////////////////// Company:// Engineer://// Create Date: 2026/07/08 19:17:36// Design Name:// Module Name: ex// Project Name:// Target Devices:// Tool Versions:// Description://// Dependencies://// Revision:// Revision 0.01 - File Created// Additional Comments:////////////////////////////////////////////////////////////////////////////////////includedefines.vmoduleex(input wire[DW-1:0]inst_i,input wire[AW-1:0]inst_addr_i,input wire reg_we_i,input wire[4:0]reg_waddr_i,input wire[DW-1:0]op1_i,input wire[DW-1:0]op2_i,input wire[DW-1:0]op1_jump_i,input wire[DW-1:0]op2_jump_i,output reg reg_we_o,output reg[4:0]reg_waddr_o,output reg[DW-1:0]reg_wdata_o,// to memoutput reg mem_we_o,output reg[AW-1:0]mem_addr_o,output reg[DW-1:0]mem_wdata_o,// jumpoutput reg jump_flag_o,output reg[AW-1:0]jump_addr_o,//for storeinput wire[DW-1:0]reg2_rdata_i);// inst slicewire[6:0]opcodeinst_i[6:0];wire[4:0]rdinst_i[11:7];wire[2:0]func3inst_i[14:12];wire[4:0]rs1inst_i[19:15];wire[4:0]rs2inst_i[24:20];wire[6:0]func7inst_i[31:25];wiresigned[DW-1:0]op1_signed$signed(op1_i);wiresigned[DW-1:0]op2_signed$signed(op2_i);wire[DW*2-1:0]mul_resultop1_i*op2_i;wire[DW*2-1:0]mulh_resultop1_signed*op2_signed;wire[DW*2-1:0]mulhsu_resultop1_signed*op2_i;always(*)begin reg_we_oreg_we_i;reg_waddr_oreg_waddr_i;reg_wdata_oZeroWord;mem_we_oWriteDisable;mem_addr_oZeroWord;mem_wdata_oZeroWord;jump_flag_oJumpDisable;jump_addr_oZeroWord;case(opcode)INST_TYPE_LUI:begin reg_wdata_oop1_iop2_i;end INST_TYPE_AUIPC:begin reg_wdata_oop1_iop2_i;end INST_TYPE_JAL:begin reg_wdata_oop1_iop2_i;jump_flag_oJumpEnable;jump_addr_oop1_jump_iop2_jump_i;end INST_TYPE_JALR:begin reg_wdata_oop1_iop2_i;jump_flag_oJumpEnable;jump_addr_oop1_jump_iop2_jump_i;end INST_TYPE_B:begin jump_addr_oop1_jump_iop2_jump_i;case(func3)INST_BEQ:begin jump_flag_o(op1_iop2_i);end INST_BNE:begin jump_flag_o(op1_i!op2_i);end INST_BLT:begin jump_flag_o(op1_signedop2_signed);end INST_BGE:begin jump_flag_o(op1_signedop2_signed);end INST_BLTU:begin jump_flag_o(op1_iop2_i);end INST_BGEU:begin jump_flag_o(op1_iop2_i);enddefault:begin end endcase end INST_TYPE_LOAD:begincase(func3)INST_LB,INST_LH,INST_LW,INST_LBU,INST_LHU:begin mem_addr_oop1_iop2_i;enddefault:begin end endcase end INST_TYPE_STORE:begincase(func3)INST_SB,INST_SH,INST_SW:begin mem_we_oWriteEnable;mem_addr_oop1_iop2_i;mem_wdata_oreg2_rdata_i;enddefault:begin end endcase end INST_TYPE_I:begincase(func3)INST_ADDI:begin reg_wdata_oop1_iop2_i;end INST_SLTI:begin reg_wdata_oop1_signedop2_signed?32d1 : 32d0;end INST_SLTIU:begin reg_wdata_oop1_iop2_i?32d1 : 32d0;end INST_XORI:begin reg_wdata_oop1_i^op2_i;end INST_ORI:begin reg_wdata_oop1_i|op2_i;end INST_ANDI:begin reg_wdata_oop1_iop2_i;end INST_SLLI:begin reg_wdata_oop1_iop2_i[4:0];end INST_SRI:beginif(func77b0000000)reg_wdata_oop1_iop2_i[4:0];elseif(func77b0100000)reg_wdata_oop1_signedop2_i[4:0];enddefault:begin end endcase end INST_TYPE_R_M:beginif(func7func7_R||func7func7_sub_sra)begincase(func3)INST_ADD_SUB:beginif(func77b0000000)reg_wdata_oop1_iop2_i;elseif(func77b0100000)reg_wdata_oop1_i-op2_i;end INST_SLL:begin reg_wdata_oop1_iop2_i[4:0];end INST_SLT:begin reg_wdata_oop1_signedop2_signed?32d1 : 32d0;end INST_SLTU:begin reg_wdata_oop1_iop2_i?32d1 : 32d0;end INST_XOR:begin reg_wdata_oop1_i^op2_i;end INST_SR:beginif(func77b0000000)reg_wdata_oop1_iop2_i[4:0];elseif(func77b0100000)reg_wdata_oop1_signedop2_i[4:0];end INST_OR:begin reg_wdata_oop1_i|op2_i;end INST_AND:begin reg_wdata_oop1_iop2_i;enddefault:begin end endcase endelseif(func7func7_M)begincase(func3)INST_MUL:begin reg_wdata_omul_result[31:0];end INST_MULH:begin reg_wdata_omulh_result[63:32];end INST_MULHSU:begin reg_wdata_omulhsu_result[63:32];end INST_MULHU:begin reg_wdata_omul_result[63:32];end INST_DIV:beginif(op2_i0)reg_wdata_o32hffff_ffff;elsereg_wdata_oop1_signed/op2_signed;end INST_DIVU:beginif(op2_i0)reg_wdata_o32hffff_ffff;elsereg_wdata_oop1_i/op2_i;end INST_REM:beginif(op2_i0)reg_wdata_oop1_i;elsereg_wdata_oop1_signed%op2_signed;end INST_REMU:beginif(op2_i0)reg_wdata_oop1_i;elsereg_wdata_oop1_i%op2_i;enddefault:begin end endcase endelsebegin end end INST_TYPE_FENCE:begin jump_flag_oJumpEnable;jump_addr_oop1_jump_iop2_jump_i;enddefault:begin end endcase end endmodule
