verilog HDLBits刷题“Bcdadd100”---Generate for-loop:100-digit BCD adder

📅 2026/7/18 11:49:31
verilog HDLBits刷题“Bcdadd100”---Generate for-loop:100-digit BCD adder
一、题目You are provided with a BCD one-digit adder named bcd_fadd that adds two BCD digits and carry-in, and produces a sum and carry-out.module bcd_fadd ( input [3:0] a, input [3:0] b, input cin, output cout, output [3:0] sum );Instantiate 100 copies of bcd_fadd to create a 100-digit BCD ripple-carry adder. Your adder should add two 100-digit BCD numbers (packed into 400-bit vectors) and a carry-in to produce a 100-digit sum and carry out.Module Declarationmodule top_module( input [399:0] a, b, input cin, output cout, output [399:0] sum );二、分析四位四位一起一共需要100次例化三、代码实现module top_module( input [399:0] a, b, input cin, output cout, output [399:0] sum ); wire [99:0]cout_mid; genvar i; generate for(i0;i100;ii1)begin:bcd_fadd if(i0) bcd_fadd bcd_inst(a[3:0],b[3:0],cin,cout_mid[0],sum[3:0]); else bcd_fadd bcd_inst(a[4*i3:4*i],b[4*i3:4*i],cout_mid[i-1],cout_mid[i],sum[4*i3:4*i]); end endgenerate assign coutcout_mid[99]; endmodule 或者 module top_module( input [399:0] a, b, input cin, output cout, output [399:0] sum ); wire [99:0]cout_mid; generate genvar i; for( i0;i99;i)begin:my_block if(i0) bcd_fadd inst(a[3:0],b[3:0],cin,cout_mid[0],sum[3:0]); else bcd_fadd inst(a[4*i3:4*i],b[4*i3:4*i],cout_mid[i-1],cout_mid[i],sum[4*i3:4*i]); end endgenerate assign coutcout_mid[99]; endmodulealways_for模块好像不能例化所以下面这种操作错误module top_module( input [399:0] a, b, input cin, output cout, output [399:0] sum ); wire [99:0]cout_mid; integer i; always(*)begin cout_mid100d0; for(i0;i100;ii1)begin if(i0)begin bcd_fadd bcd_inst(a[3:0],b[3:0],cin,cout_mid[0],sum[3:0]); end else bcd_fadd bcd_inst(a[4*i3:4*i],b[4*i3:4*i],cout_mid[i-1],cout_mid[i],sum[4*i3:4*i]); end end assign coutcout_mid[99]; endmodule