一、数据类型语法说明代码示例logic [N-1:0] name4态逻辑向量可驱动、可赋值模块端口推荐类型logic [31:0] data_l;integer name32位有符号整数4态默认符号用于计数与状态integer data_i;bit name2态单比特仅0/1仿真高效用于验证bit a;byte name2态8位有符号整数byte b;shortint name2态16位有符号整数shortint c;int name2态32位有符号整数int e;longint name2态64位有符号整数longint d;wire [N-1:0] name线网类型4态支持多驱动如inout总线必须用于端口双向信号wire [7:0] bus_data;tri [N-1:0] name三态线网语义明确的多驱动类型等价于wire用于显式表达三态行为tri [7:0] tri_bus;time name64位无符号整数4态专用于仿真时间戳time current_time $time;real name双精度浮点数64位2态高精度计算不支持X/Zreal voltage_val 3.3;shortreal name单精度浮点数32位2态内存节省类似C的floatshortreal gain 0.95;string name动态字符串用于日志、文件名、调试信息string test_name ALU_Test;二、数组语法说明代码示例type name [Size]‌定宽数组静态数组‌编译时确定大小内存连续或非连续取决于是否 packed。int mem [0:1023];type name []‌动态数组‌运行时分配大小使用new[]操作符。int dyn_arr []; dyn_arr new;type name [$]‌队列Queue‌先进先出FIFO结构支持push_back,pop_front等操作无需预先分配大小。int fifo [$]; fifo.push_back(5);type name [IndexType]‌关联数组Associative Array‌稀疏数组索引可以是任意类型如 int, string仅存储被赋值的元素。int assoc_arr [int]; assoc_arr 1;type [Msbs:Lsbs] name [Dims]‌合并数组Packed Array‌作为单个向量处理位宽连续常用于硬件信号映射。bit [7:0] [3:0] bytes; // 32位向量三、结构化类型语法说明代码示例typedef type name类型别名typedef logic [3:0] u4_t;typedef enum base_type {item,...} name枚举类型typedef enum logic [1:0] {IDLE,BUSY,DONE,ERR} state_t;typedef struct packed {...} name压缩结构体typedef struct packed {logic [31:0] addr; ...} bus_req_t;struct_name.member结构体成员访问req.addr 32h1000_0000;struct_name {val1, val2, ...}结构体整体拼接赋值req {32h1000_0000, 32hAAAA_0000, 1b1};typedef union packed {...} name压缩联合体typedef union packed {logic [31:0] word; ...} data_packet_t;union_name.member联合体成员访问uu_pkt.bytes[3] 8haa;四、过程块语法说明代码示例always_comb组合逻辑块always_comb begincomb_out !comb_in;endalways_ff时序逻辑块异步复位always_ff (posedge clk or posedge rst)begin ... endalways_latch锁存器逻辑块always_latch beginif(latch_in)latch_out 1b1;end五、高级控制语句语法说明代码示例foreach (array[index]) begin ... end数组遍历foreach (mem[i]) begin ... endcontinue跳过本次循环剩余语句if(i 6) continue;break跳出整个循环if(i 2) break;unique case (expr) ... endcase唯一分支互斥unique case (state_n) ... endcasepriority case (expr) ... endcase优先级分支priority case (1b1) ... endcaseunique if ... else if ... else唯一条件分支unique if(un_x) ... else if(un_y) ... else;priority if ... else if ...优先级条件分支priority if(pr_x) ... else if(pr_y) ...六、接口Interface语法说明代码示例interface name(input ports); ... endinterface接口声明interface simple_bus_if(input logic clk); ... endinterfacemodport name (direction sig_list)接口方向视图modport DUT (input valid, addr, data; output ready);module_name.interface_port_name接口端口连接my_dut u_dut (.bus_if(intf.DUT));interface_instance.modport_name通过modport访问接口simple_bus_if.DUT bus_if模块端口声明bus_if.signal_name访问接口内部信号bus_if.valid,bus_if.ready七、SVA 断言语法说明代码示例assert(expr) else $error(...)立即断言assert(req ! 1bx) else $error(req is X);property name; ... endproperty属性声明property p_name; (posedge clk) disable iff(!rst_n) req 1b1; endpropertyassert property (prop) else ...并发断言assert property (p_name) else $error(failed);(posedge clk)时钟事件控制(posedge clk) disable iff(!rst_n)disable iff(cond)复位屏蔽disable iff(!rst_n)A |- B重叠蕴含req |- ##3 ackA | B非重叠蕴含(valid !ready) | valid## N延迟N个周期req |- ##3 ack##[m:n]延迟范围req |- ##[1:5] acksig[*N]连续重复N次busy[*3]sig[*m:n]连续重复范围data_valid[*1:5]sig[-N]跟随重复N次非连续最后一拍结束ready[-3]sig[N]非连续重复可拖尾ready[3]$rose(sig)检测上升沿$rose(req)$fell(sig)检测下降沿$stable(sig)检测信号不变$stable(data)$past(sig, N)取N拍前的值$isunknown(sig)检测X/Z$isunknown(req)seq1 within seq2序列包含(read ##1 read) within (busy[*4])seq1 intersect seq2序列交集同时开始结束(data_valid[*1:$]) intersect (transfer_en[*5])cover property (prop)覆盖率收集cover property ((posedge clk) $rose(req));assume property (prop)输入约束bind target_module checker_module #(...) inst_name (.*)外部绑定断言bind fifo fifo_sva #(.DEPTH(16)) u_fifo_sva (.*);八、Package语法说明代码示例package name; ... endpackage包声明package bus_pkg; ... endpackageimport pkg_name::*导入包所有内容import bus_pkg::*;pkg_name::identifier路径引用包内容bus_pkg::DATA_WIDTHfunction automatic ret_type name(args); ... endfunction包内自动函数function automatic data_t saturation_clip(logic [31:0] din); ... endfunctionlocalparam type name value包内局部常量localparam int DATA_WIDTH 16;typedef ...包内类型定义typedef logic [DATA_WIDTH-1:0] data_t;