1、题目2、代码module top_module( input clk, input reset, // Active-high synchronous reset to 32h1 output reg [31:0] q ); reg [31:0] next_q; always (*) begin // 组合逻辑计算下一状态 next_q {q[0],q[31:1]}; // 默认右移next_q[i] q[i1] next_q[31] q[0]; next_q[21] q[22] ^ q[0]; next_q[1] q[2] ^ q[0]; next_q[0] q[1] ^ q[0]; end always(posedge clk)begin if(reset) q 32h1; else q next_q; end endmodule