verilog HDLBits刷题[Finite State Machines]“Fsm2s”---Simple FSM2(synchronous reset)
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1、题目This is a Moore state machine with two states, two inputs, and one output. Implement this state machine.This exercise is the same as fsm2, but using synchronous reset.2、代码module top_module( input clk, input reset, // Asynchronous reset to OFF input j, input k, output out); // parameter OFF0, ON1; reg state, next_state; always (*) begin case(state) OFF:if (j0) next_stateOFF; else next_stateON; ON:if (k0) next_stateON; else next_stateOFF; endcase end always (posedge clk) begin if(reset) stateOFF; else statenext_state; end assign out (state ON); endmodule3、结果
![verilog HDLBits刷题[Finite State Machines]“Fsm2”---Simple FSM2(asynchronous reset)](http://pic.xiahunao.cn/yaotu/verilog HDLBits刷题[Finite State Machines]“Fsm2”---Simple FSM2(asynchronous reset))
