拓扑模式的Design Compiler NXT在2019版本针对ARM的高性能处理器内核综合引入了一个功能用户可以使用set_hpc_options命令针对内核应用推荐的设置。这些设置包括针对特定内核的应用变量设置、针对特定内核的解组策略选择、针对特定内核的路径分组方式。它们与QuickStart Implementation Kits即QIK中的设置类似QIK是Synopsys与ARM合作的结果针对特定ARM内核提供以下内容工具设置脚本、基础布图规划、设计约束以及相关文档。在使用set_hpc_options命令之前必须先使用set_technology命令指定工艺节点因为有些设置与工艺节点相关在全量综合(compile_ultra -spg)和增量综合(compile_ultra -spg -incr)之前需要使用set_hpc_options命令因为有些设置与阶段相关。下面给出了Flow示意图和参考脚本。图1 HPC Megaswitch Flow# read the setup, design, and constraints set_technology -node 7 set_hpc_options -core A55 -stage compile compile_ultra -spg ... insert_dft ... set_hpc_options -core A55 -stage compile_inc compile_ultra -spg -incremental如果想知道set_hpc_options命令执行了哪些设置使用-report_only选项即可如下所示。dcnxt_shell-topo set_hpc_options -report_only set_hpc_options A55-1.0 Current design is TOP. HPC specific settings for core: A55 HPC core: A55 Stage: compile Version: 1.03 Current design is TOP. Current design is TOP. HPC-INFO: Apply compile settings... HPC-INFO: defining Ananke Path Groups proc set_ananke_path_groups {} { global synopsys_program_name set clock_ports [get_ports [get_attribute [get_clocks -f defined(sources)] sources]] if {$synopsys_program_name ! dc_shell} { set macro_cells [get_cells -hier * -filter is_memory_celltrue] } else { set macro_cells [all_macro_cells] } if {$synopsys_program_name pt_shell} { set all_icgs [get_cells -hierarchical -filter is_integrated_clock_gating_celltrue] set arch_cgs [filter_collection $all_icgs full_name~*HANDINST*] set pwrc_cgs [remove_from_collection $all_icgs $arch_cgs] } elseif {$synopsys_program_name ! dc_shell} { set all_icgs [get_flat_cells -filter is_integrated_clock_gating_celltrue] set arch_cgs [filter_collection $all_icgs full_name~*HANDINST*] set pwrc_cgs [remove_from_collection $all_icgs $arch_cgs] } else { set timing_separate_clock_gating_group false set all_icgs [get_flat_cells -filter clock_gating_integrated_cell~*latch*] set pwrc_cgs [filter_collection $all_icgs clock_gating_latch_stylelatch] set arch_cgs [remove_from_collection $all_icgs $pwrc_cgs] } set all_regs [remove_from_collection [all_registers] $macro_cells] set core_regs [remove_from_collection $all_regs $all_icgs] set non_clk_inputs [remove_from_collection [all_inputs] $clock_ports] group_path -name Inputs -from $non_clk_inputs group_path -name Outputs -to [all_outputs] group_path -name Reg2ArchICGs -from $all_regs -to $arch_cgs if { [sizeof_collection $pwrc_cgs] 0 } { group_path -name Reg2PwrCICGs -from $all_regs -to $pwrc_cgs } group_path -name In2ICGs -from $non_clk_inputs -to $all_icgs if {$synopsys_program_name ! dc_shell} { set ram_clocks [get_pins -of_objects $macro_cells -filter pin_directionin is_clock_pintrue] } else { set ram_clocks [get_pins -of_objects $macro_cells -filter pin_directionin (is_clock_pintrue || pin_on_clock_network_per_scntrue)] } set ram_endpoints [remove_from_collection [get_pins -of_objects $macro_cells -filter pin_directionin] $ram_clocks] set ram_startpoints [get_pins -of_objects $macro_cells -filter pin_directionout] append_to_collection ram_startpoints $ram_clocks set CBSYS_REGS [filter_collection $all_regs full_name~u_cb_sys*] set CB_REGS [filter_collection $all_regs full_name~u_vcpu?u_cb_cpu*] set GIC_REGS [filter_collection $all_regs full_name~u_vcpu?u_cpu?u_ananke_gic*] set IFU_REGS [filter_collection $all_regs full_name~u_vcpu?u_cpu?u_ananke_ifu*] set IFU_PF_REGS [filter_collection $IFU_REGS full_name~u_vcpu?u_cpu?u_ananke_ifu?u_pf?*] set IFU_CTL_REGS [filter_collection $IFU_REGS full_name~u_vcpu?u_cpu?u_ananke_ifu?u_ctl?*] set DCU_REGS [filter_collection $all_regs full_name~u_vcpu?u_cpu?u_ananke_dcu?*] set BIU_REGS [filter_collection $all_regs full_name~u_vcpu?u_cpu?u_ananke_biu?*] set DPU_REGS [filter_collection $all_regs full_name~u_vcpu?u_cpu?u_ananke_dpu?*] set DPU_DBG_REGS [filter_collection $all_regs full_name~*?u_dpu_dbg?*] set DPU_DE_REGS [filter_collection $all_regs full_name~*?u_dpu_de?*] set DPU_CP_REGS [filter_collection $DPU_REGS full_name~*?u_dpu_cp?* full_name!~*?u_dpu_cpsr?*] set DPU_CPSR_REGS [filter_collection $DPU_REGS full_name~*?u_dpu_cpsr?*] set DPU_CTL_REGS [filter_collection $DPU_REGS full_name~*?u_dpu_ctl?*] set DPU_DP_REGS [filter_collection $DPU_REGS full_name~*?u_dpu_dp?*] set DPU_FPU_REGS [filter_collection $DPU_REGS full_name~*FPU??u_dpu_fp?*] set DPU_FPUDP_REGS [filter_collection $DPU_FPU_REGS full_name~*?u_dpu_fp_dp?*] set DPU_DPALU_REGS [filter_collection $DPU_FPUDP_REGS full_name~*?u_ananke_dpu_fp_alu??*] set DPU_CRYPT_REGS [filter_collection $DPU_FPUDP_REGS full_name~*?g_crypto?u_crypto?*] set DPU_FPURBK_REGS [filter_collection $DPU_FPU_REGS full_name~*?u_dpu_fp_regbank?*] set DPU_LDST_REGS [filter_collection $DPU_REGS full_name~*?u_dpu_ldst?*] set DPU_RGBNK_REGS [filter_collection $DPU_REGS full_name~*?u_dpu_regbank?*] set DPU_STORE_REGS [filter_collection $DPU_REGS full_name~*u_store??*] set ETM_REGS [filter_collection $all_regs full_name~u_vcpu?u_cpu?u_ananke_etm?*] set GIC_REGS [filter_collection $all_regs full_name~u_vcpu?u_cpu?u_ananke_gic?*] set TLB_REGS [filter_collection $all_regs full_name~u_vcpu?u_cpu?u_ananke_tlb?*] set TLBTAG_REGS [filter_collection $TLB_REGS full_name~*u_tlb_tag*] set TLBTAGDB_REGS [filter_collection $TLBTAG_REGS full_name~*u_tlb_data_bank*] set TLBPAGE_REGS [filter_collection $TLB_REGS full_name~*u_tlb_pagewalk*] set TLBMBIST_REGS [filter_collection $TLB_REGS full_name~*mbist*] set TLBOTHER_REGS [remove_from_collection $TLB_REGS $TLBTAG_REGS] set STB_REGS [filter_collection $all_regs full_name~u_vcpu?u_cpu?u_ananke_stb?*] set L2_REGS [filter_collection $all_regs full_name~u_vcpu?u_cpu?u_ananke_l2?*] set L2_TAG_REGS [filter_collection $L2_REGS full_name~*u_l2_tag*] group_path -name BIU -from $BIU_REGS -to $BIU_REGS group_path -name BIU2DCU -from $BIU_REGS -to $DCU_REGS group_path -name BIU2DPU -from $BIU_REGS -to $DPU_REGS group_path -name BIU2IFU -from $BIU_REGS -to $IFU_REGS group_path -name BIU2L2 -from $BIU_REGS -to $L2_REGS group_path -name BIU2TLB -from $BIU_REGS -to $TLB_REGS group_path -name BIU2STB -from $BIU_REGS -to $STB_REGS group_path -name CB -from $CB_REGS -to $CB_REGS group_path -name CB2BIU -from $CB_REGS -to $BIU_REGS group_path -name CB2DCU -from $CB_REGS -to $DCU_REGS group_path -name CB2DPU -from $CB_REGS -to $DPU_REGS group_path -name CB2ETM -from $CB_REGS -to $ETM_REGS group_path -name CB2IFU -from $CB_REGS -to $IFU_REGS group_path -name CB2L2 -from $CB_REGS -to $L2_REGS group_path -name CBSYS -from $CBSYS_REGS -to $CBSYS_REGS group_path -name CB2CBSYS -from $CB_REGS -to $CBSYS_REGS group_path -name GIC -from $GIC_REGS -to $GIC_REGS group_path -name L22CB -from $L2_REGS -to $CB_REGS group_path -name IFU -from $IFU_REGS -to $IFU_REGS group_path -name IFU2BIU -from $IFU_REGS -to $BIU_REGS group_path -name IFU2DCU -from $IFU_REGS -to $DCU_REGS group_path -name IFU2DPU -from $IFU_REGS -to $DPU_REGS group_path -name IFU2L2 -from $IFU_REGS -to $L2_REGS group_path -name IFU2STB -from $IFU_REGS -to $STB_REGS group_path -name IFU2TLB -from $IFU_REGS -to $TLB_REGS group_path -name IFU_PF -from $IFU_PF_REGS -to $IFU_PF_REGS group_path -name DCU -from $DCU_REGS -to $DCU_REGS group_path -name DCU2CB -from $DCU_REGS -to $CB_REGS group_path -name DCU2BIU -from $DCU_REGS -to $BIU_REGS group_path -name DCU2DPU -from $DCU_REGS -to $DPU_REGS group_path -name DCU2IFU -from $DCU_REGS -to $IFU_REGS group_path -name DCU2L2 -from $DCU_REGS -to $L2_REGS group_path -name DCU2STB -from $DCU_REGS -to $STB_REGS group_path -name DCU2TLB -from $DCU_REGS -to $TLB_REGS group_path -name DPU -from $DPU_REGS -to $DPU_REGS group_path -name DPU_CP_CTL -from $DPU_CP_REGS -to $DPU_CTL_REGS group_path -name DPU_CP_LDST -from $DPU_CP_REGS -to $DPU_LDST_REGS group_path -name DPU_CPSR_CTL -from $DPU_CPSR_REGS -to $DPU_CTL_REGS group_path -name DPU_CPSR_DE -from $DPU_CPSR_REGS -to $DPU_DE_REGS group_path -name DPU_CPSR_RGBNK -from $DPU_CPSR_REGS -to $DPU_RGBNK_REGS group_path -name DPU_CPSR_LDST -from $DPU_CPSR_REGS -to $DPU_LDST_REGS group_path -name DPU_CTL -from $DPU_CTL_REGS -to $DPU_CTL_REGS group_path -name DPU_CTL_DP -from $DPU_CTL_REGS -to $DPU_DP_REGS group_path -name DPU_CTL_FPU -from $DPU_CTL_REGS -to $DPU_FPU_REGS group_path -name DPU_CTL_LDST -from $DPU_CTL_REGS -to $DPU_LDST_REGS group_path -name DPU_CTL_FPUDP -from $DPU_CTL_REGS -to $DPU_FPUDP_REGS group_path -name DPU_CRYPT_ALU -from $DPU_CRYPT_REGS -to $DPU_DPALU_REGS group_path -name DPU_FPUCRYPT -from $DPU_CRYPT_REGS -to $DPU_CRYPT_REGS group_path -name DPU_FPURBK_DP -from $DPU_FPURBK_REGS -to $DPU_FPUDP_REGS group_path -name DPU_DBG_CTL -from $DPU_DBG_REGS -to $DPU_CTL_REGS group_path -name DPU_DBG_LDST -from $DPU_DBG_REGS -to $DPU_LDST_REGS group_path -name DPU_DE -from $DPU_DE_REGS -to $DPU_DE_REGS group_path -name DPU_DE_CTL -from $DPU_DE_REGS -to $DPU_CTL_REGS group_path -name DPU_DE_LDST -from $DPU_DE_REGS -to $DPU_LDST_REGS group_path -name DPU_DE_RGBNK -from $DPU_DE_REGS -to $DPU_RGBNK_REGS group_path -name DPU_DP -from $DPU_DP_REGS -to $DPU_DP_REGS group_path -name DPU_DP_FPU -from $DPU_DP_REGS -to $DPU_FPU_REGS group_path -name DPU_FPU -from $DPU_FPU_REGS -to $DPU_FPU_REGS group_path -name DPU_FPU_CTL -from $DPU_FPU_REGS -to $DPU_CTL_REGS group_path -name DPU_FPU_DP -from $DPU_FPU_REGS -to $DPU_DP_REGS group_path -name DPU_FPUDP -from $DPU_FPUDP_REGS -to $DPU_FPUDP_REGS group_path -name DPU_FPUDP_ALU -from $DPU_DPALU_REGS -to $DPU_DPALU_REGS group_path -name DPU_FPUDP_RGBNK -from $DPU_FPUDP_REGS -to $DPU_FPURBK_REGS group_path -name DPU_FPURGBNK -from $DPU_FPURBK_REGS -to $DPU_FPURBK_REGS group_path -name DPU_FPU_STORE -from $DPU_FPU_REGS -to $DPU_STORE_REGS group_path -name DPU_RGBNK -from $DPU_RGBNK_REGS -to $DPU_RGBNK_REGS group_path -name DPU2BIU -from $DPU_REGS -to $BIU_REGS group_path -name DPU2CB -from $DPU_REGS -to $CB_REGS group_path -name DPU2ETM -from $DPU_REGS -to $ETM_REGS group_path -name DPU2GIC -from $DPU_REGS -to $GIC_REGS group_path -name DPU2IFU -from $DPU_REGS -to $IFU_REGS group_path -name DPU2L2 -from $DPU_REGS -to $L2_REGS group_path -name DPU2STB -from $DPU_REGS -to $STB_REGS group_path -name ETM -from $ETM_REGS -to $ETM_REGS group_path -name STB -from $STB_REGS -to $STB_REGS group_path -name STB2BIU -from $STB_REGS -to $BIU_REGS group_path -name STB2DCU -from $STB_REGS -to $DCU_REGS group_path -name STB2DPU -from $STB_REGS -to $DPU_REGS group_path -name STB2L2 -from $STB_REGS -to $L2_REGS group_path -name STB2TLB -from $STB_REGS -to $TLB_REGS group_path -name MEM2IFU_PF -from $ram_clocks -to $IFU_PF_REGS group_path -name MEM2IFU_CTL -from $ram_clocks -to $IFU_CTL_REGS group_path -name MEM2TLB -from $ram_clocks -to $TLBOTHER_REGS group_path -name MEM2STB -from $ram_clocks -to $STB_REGS group_path -name L2 -from $L2_REGS -to $L2_REGS group_path -name L22DCU -from $L2_REGS -to $DCU_REGS group_path -name L22DPU -from $L2_REGS -to $DPU_REGS group_path -name MEM2L2 -from $ram_clocks -to $L2_REGS group_path -name L2Tag -from $L2_TAG_REGS -to $L2_TAG_REGS group_path -name L22BIU -from $L2_REGS -to $BIU_REGS group_path -name DPU2DCU -from $DPU_REGS -to $DCU_REGS group_path -name DPU2TLB -from $DPU_REGS -to $TLBOTHER_REGS group_path -name TLB -from $TLBOTHER_REGS -to $TLBOTHER_REGS group_path -name TLB2BIU -from $TLB_REGS -to $BIU_REGS group_path -name TLB2DCU -from $TLB_REGS -to $DCU_REGS group_path -name TLB2DPU -from $TLB_REGS -to $DPU_REGS group_path -name TLB2IFU -from $TLB_REGS -to $IFU_REGS group_path -name TLB2L2 -from $TLB_REGS -to $L2_REGS group_path -name TLB2STB -from $TLB_REGS -to $STB_REGS # Mem Start and End Points set L1D_DATARAM_endpoints [filter_collection $ram_endpoints full_name~*ddata_bank*] set L1D_DATARAM_startpoints [filter_collection $ram_startpoints full_name~*ddata_bank*] set L1I_DATARAM_endpoints [filter_collection $ram_endpoints full_name~*idata_bank*] set L1I_DATARAM_startpoints [filter_collection $ram_startpoints full_name~*idata_bank*] set L1_TAGRAM_endpoints [filter_collection $ram_endpoints full_name~*itag_ram*] set L1_TAGRAM_startpoints [filter_collection $ram_startpoints full_name~*itag_ram*] set L2_DATARAM_endpoints [filter_collection $ram_endpoints full_name~*l2_dataram*] set L2_DATARAM_startpoints [filter_collection $ram_startpoints full_name~*l2_dataram*] set L2_TAGRAM_endpoints [filter_collection $ram_endpoints full_name~*l2_tagram*] set L2_TAGRAM_startpoints [filter_collection $ram_startpoints full_name~*l2_tagram*] set L2DB_DATARAM_endpoints [filter_collection $ram_endpoints full_name~*l2db_ram*] set L2DB_DATARAM_startpoints [filter_collection $ram_startpoints full_name~*l2db_ram*] set TLB_DATARAM_endpoints [filter_collection $ram_endpoints full_name~*tlb_data_bank*] set TLB_DATARAM_startpoints [filter_collection $ram_startpoints full_name~*tlb_data_bank*] set TLB_TAGRAM_endpoints [filter_collection $ram_endpoints full_name~*tlb_tag_bank*] set TLB_TAGRAM_startpoints [filter_collection $ram_startpoints full_name~*tlb_tag_bank*] set DIRTY_RAM_endpoints [filter_collection $ram_endpoints full_name~*dirty_rams*] set DIRTY_RAM_startpoints [filter_collection $ram_startpoints full_name~*dirty_rams*] set BTAC_RAM_endpoints [filter_collection $ram_endpoints full_name~*btac_stg*] set BTAC_RAM_startpoints [filter_collection $ram_startpoints full_name~*btac_stg*] set L2_VICTIMRAM_endpoints [filter_collection $ram_endpoints full_name~*l2_victimram*] set L2_VICTIMRAM_startpoints [filter_collection $ram_startpoints full_name~*l2_victimram*] group_path -name REG2L1IDATARAM -to $L1D_DATARAM_endpoints group_path -name REG2L1DDATARAM -to $L1I_DATARAM_endpoints group_path -name REG2L1TAGRAM -to $L1_TAGRAM_endpoints group_path -name REG2L2DATARAM -to $L2_DATARAM_endpoints group_path -name REG2L2TAGRAM -to $L2_TAGRAM_endpoints group_path -name REG2L2DBDATARAM -to $L2DB_DATARAM_endpoints group_path -name REG2TLBDATARAM -to $TLB_DATARAM_endpoints group_path -name REG2TLBTAGRAM -to $TLB_TAGRAM_endpoints group_path -name REG2DIRTYRAM -to $DIRTY_RAM_endpoints group_path -name REG2BTACRAM -to $BTAC_RAM_endpoints group_path -name REG2L2VICTIMRAM -to $L2_VICTIMRAM_endpoints group_path -name L1DDATA2REG -from $L1D_DATARAM_startpoints group_path -name L1IDATA2REG -from $L1I_DATARAM_startpoints group_path -name L1TAGRAM2REG -from $L1_TAGRAM_startpoints group_path -name L2DATARAM2REG -from $L2_DATARAM_startpoints group_path -name L2TAGRAM2REG -from $L2_TAGRAM_startpoints group_path -name L2DBDATARAM2REG -from $L2DB_DATARAM_startpoints group_path -name TLBDATARAM2REG -from $TLB_DATARAM_startpoints group_path -name TLBTAGRAM2REG -from $TLB_TAGRAM_startpoints group_path -name DIRTYRAM2REG -from $DIRTY_RAM_startpoints group_path -name BTACRAM2REG -from $BTAC_RAM_startpoints group_path -name L2VICTIMRAM2REG -from $L2_VICTIMRAM_startpoints } proc set_ananke_compile_directives {} { set tech [get_attribute -quiet [current_design] technology_node] set metrics [get_attribute -quiet [current_design] metric_target] set keep_hierarchies [list u_cb_sys u_vcpu u_vcpu/u_cb_cpu u_vcpu/u_cb_cpu/u_cpu_crg u_vcpu/u_cpu u_vcpu/u_cpu/u_ananke_tlb u_vcpu/u_cpu/u_ananke_tlb/u_tlb_tag_data_ram u_vcpu/u_cpu/u_ananke_biu u_vcpu/u_cpu/u_ananke_stb u_vcpu/u_cpu/u_ananke_dpu u_vcpu/u_cpu/u_ananke_dcu u_vcpu/u_cpu/u_ananke_dcu/u_ananke_dcu_rams u_vcpu/u_cpu/u_ananke_dcu/u_ananke_dcu_rams/u_ananke_l1d_datarams u_vcpu/u_cpu/u_ananke_dcu/u_ananke_dcu_rams/u_ananke_l1d_tag_dirty_rams u_vcpu/u_cpu/u_ananke_ifu u_vcpu/u_cpu/u_ananke_ifu/u_pf u_vcpu/u_cpu/u_ananke_ifu/u_pf/u_pf_btac u_vcpu/u_cpu/u_ananke_ifu/u_ananke_l1i_datarams u_vcpu/u_cpu/u_ananke_ifu/u_ananke_l1i_tagrams u_vcpu/u_cpu/u_ananke_l2 u_vcpu/u_cpu/u_ananke_l2/u_l2_ramctl_wrapper u_vcpu/u_cpu/u_ananke_l2/u_l2_tagctl_wrapper u_vcpu/u_cpu/u_ananke_l2/u_l2_victimctl_wrapper u_vcpu/u_cpu/u_ananke_l2/u_l2_l2dbs_wrapper u_vcpu/u_cpu/u_ananke_l2/u_l2_l2dbs_wrapper/u_l2_l2dbrams u_vcpu/u_cpu/u_ananke_l2/u_l2_victimctl_wrapper/g_l2_rams?u_ananke_l2_victimrams ] foreach hierarchy $keep_hierarchies { echo INFO: Do not ungroup $hierarchy set_ungroup [get_cells -hier -filter full_name~$hierarchy] false } # Skip clk gate checks if {$tech!16} { set no_clk_gate_regs [get_cells -hier -filter full_name~u_cb_sys*payload*] append_to_collection no_clk_gate_regs [get_cells -hier -filter full_name~u_cb_sys*rptr*] append_to_collection no_clk_gate_regs [get_cells -hier -filter full_name~u_vcpu*wptr*] if {[sizeof $no_clk_gate_regs]0} {set_clock_gating_objects -exclude $no_clk_gate_regs} } # Specify logic to size_only set all_size_only_cells [get_cells -quiet -hier -filter full_name~*HANDINST*] if {[sizeof $all_size_only_cells]0} {set_size_only $all_size_only_cells true} # multibit set no_mb_hierarchies [list ] foreach no_mb_hier $no_mb_hierarchies { echo INFO: Removing multibit specification for $no_mb_hier cells remove_multibit [get_cells -hier -filter full_name~${no_mb_hier}*] } } Report only: set_app_var auto_insert_level_shifters_on_clocks all Report only: set_app_var compile_advanced_fix_multiple_port_nets true Report only: set_app_var compile_enable_register_merging_with_exceptions false Report only: set_app_var compile_enable_register_merging false Report only: set_app_var compile_prefer_mux true Report only: set_app_var compile_register_replication_across_hierarchy true Report only: set_app_var compile_timing_high_effort_tns true Report only: set_app_var compile_timing_high_effort true Report only: set_app_var dct_placement_ignore_scan true Report only: set_app_var enable_recovery_removal_arcs true Report only: set_app_var placer_channel_detect_mode true Report only: set_app_var placer_enable_enhanced_router true Report only: set_app_var placer_gated_register_area_multiplier 8 Report only: set_app_var placer_max_cell_density_threshold 0.50 Report only: set_app_var placer_tns_driven true Report only: set_app_var power_cg_physically_aware_cg true Report only: set_app_var psynopt_density_limit 0.90 Report only: set_app_var psynopt_tns_high_effort true Report only: set_app_var report_default_significant_digits 4 Report only: set_app_var spg_enable_zroute_layer_promotion false Report only: set_app_var timing_scgc_override_library_setup_hold false Report only: set_app_var timing_separate_clock_gating_group true Report only: set_auto_disable_drc_nets -scan false -constant false Report only: set_compile_spg_mode ICC2 Report only: set_register_merging [current_design] false