verilog HDLBits刷题[Bulid a circuit from a simulation waveform]“Sim/circuit7”---Sequential circuit7
1、题目2、分析a为0时,q为1,当a变为1时,q在下一个时钟周期变为03、代码module top_module (input clk,input a,output q );always (posedge clk) beginq < (~ a);end
endmodule4、结果
2026/8/11 22:03:14