verilog HDLBits刷题[Verification:Writing Testbenches]“Tb/tb1”---Testbench1
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1、题目2、分析写一个testbench产生如图A和B信号,注意时间的相对性3、代码module top_module ( output reg A, output reg B );// // generate input patterns here initial begin A 1b0; B 1b0; # 10 A 1b1; # 5 B 1b1; # 5 A 1b0; # 20 B 1b0; end endmodule4、结果
