简单流水CPU(只考虑数据冲突)
一、CPU设计框图二、各模块代码1. 流水段寄存器IF/IDtimescale 1ns / 1psmodule if_id(input clk,input resetn,input enable,input [31:0] PC,input [31:0] IR,output [31:0] IF_ID_PC,output [31:0] IF_ID_IR
);reg [31:0] IF_ID_1PC,IF_ID_1IR;always (posedge clk or neged…
2026/8/14 5:34:48