verilog HDLBits刷题[Finite State Machines]“Fsm2s”---Simple FSM2(synchronous reset)
1、题目
This is a Moore state machine with two states, two inputs, and one output. Implement this state machine.
This exercise is the same as fsm2, but using synchronous reset. 2、代码
module top_module(input clk,input reset, // Asynchronous reset to…
2026/7/27 23:17:47